Cadence and Nvidia launch Maestro AI models for chip design automation
Cadence Systems and Nvidia introduced the Maestro AI model family this week, designed to accelerate electronic design automation (EDA) tasks. The models, fine-tuned on Nvidia’s Nemotron foundation models, integrate with Cadence’s existing tools like AuraStack (packaging/PCB), ChipStack (SoC design), InnoStack (PHY routing), and ViraStack (analog circuits). Early tests claim up to 30% better…
Key points
- Cadence and Nvidia unveil **Maestro AI models**, fine-tuned on Nvidia’s Nemotron for EDA tasks like SoC design and analog circuits
- Early tests show **up to 30% better output quality** and **up to 5x token efficiency** vs. general-purpose LLMs, per Cadence
- Maestro integrates with Cadence’s existing **AI Super Agents** (AuraStack, ChipStack, etc.) and offers **customization via managed services**
The Maestro platform also offers customization via managed services, allowing customers to fine-tune models on their own data. Access is available via API, secure VPC, or on-premises (with hardware requirements). Nvidia’s broader push into AI-driven HPC aligns with this effort, as both companies leverage AI agents to streamline workflows—mirroring trends in public research, like Sandia National Labs’ self-driving lab experiments. Cadence estimates 20–30% of chips in development already use AI-assisted design, signaling growing adoption in semiconductor workflows.
The story so far
2 episodes →- Cadence and Nvidia launch Maestro AI models for chip design automationthis story
Cadence, Nvidia Unveil New AI Models To Put EDA On Autopilot
nextplatform.com · 26 October 2026
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