Cadence, Synopsys, Siemens claim Level 5 autonomy in chip design agents by 2026
Three major chip design software firms—Cadence, Synopsys, and Siemens EDA—are racing to integrate agentic AI into their Electronic Design Automation (EDA) tools. Each claims progress toward Level 5 autonomy, where agents handle tasks from chip specifications to verified layouts with minimal human input. Cadence’s ChipStack demoed a bounded Level 5 in June, while Synopsys and Siemens tout L5…
Key points
- Cadence, Synopsys, and Siemens claim **Level 5 autonomy** in their EDA agents by 2026, though definitions differ and benchmarks are vendor-reported
- Synopsys says RTL validation could be **50x faster** with 20% improved coverage, while Cadence claims **40x speedups** in verification loops for early users
- Empyrean’s agent reportedly cuts layout tasks from **four weeks to one day**, but all claims lack independent verification or named production customers
The agents rely on existing deterministic engines (like Xcelium or Questa) for verification, iterating through loops where AI proposes changes and tools validate them. Front-end gains—such as 50x faster RTL validation (Synopsys) or 40x speedups in verification loops (Cadence)—are more measurable than back-end improvements, which face physics-based constraints. Early access programs (e.g., Cadence’s ChipStack since February) and partnerships with Nvidia’s Nemotron and OpenShell sandbox aim to ensure safety. General availability is promised by year-end, but real-world adoption remains unproven beyond trials with customers like Nvidia, Qualcomm, and MediaTek.
The story so far
5 episodes →- Cadence, Synopsys, Siemens claim Level 5 autonomy in chip design agents by 2026this story
The state of agentic AI in chip design tools in 2026
Tom's Hardware · 30 September 2026
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