OpenAI VP details Jalapeño ASIC’s AI-assisted design and efficiency focus
OpenAI’s VP of Hardware, Richard Ho, discussed the company’s custom Jalapeño inference ASIC in an interview with Tom’s Hardware, emphasizing efficiency and AI-driven design. The chip, revealed at Hot Chips 2026, cuts design timelines to nine months from scratch—half the industry standard—thanks to AI tools like Codex and GPT-6 Astra optimizing microarchitecture and compiler work. Ho clarified…
Key points
- Jalapeño’s design took **nine months** from scratch, aided by AI tools like Codex and GPT-6 Astra, cutting industry timelines in half
- OpenAI prioritizes internal compute needs but could license Jalapeño’s design flow to the industry, per Ho’s comments
- Pairing Jalapeño with Nvidia’s Turing (not Vera) balances speed and risk; speculative decode is implemented but unbenchmarked
Ho also addressed supply constraints, noting OpenAI secured early commitments for wafers and memory. The chip pairs with Nvidia’s Turing (not Vera) for pragmatic de-risking. Future iterations depend on tech readiness (e.g., HBM generations, optical links). Jalapeño’s speculative decode is implemented but unbenchmarked; multi-token prediction could boost performance 3–5x. Rollout begins in 2027, with Jalapeño Gen 2 in development but no fixed cadence—tape-outs will target step-function improvements, not calendar schedules.
Model page: GPT-6 Astra →
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OpenAI Jalapeño design interview transcript
Tom's Hardware · 28 September 2026
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This text was published by Tom's Hardware and written by Jake Roach. It is reproduced here with attribution so you can read it in full; the rights remain with the publisher. Read it at the source ↗
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