Synopsys and TSMC expand AI design collaborations to A14 and co-packaged optics
Synopsys announced on September 23, 2026 a series of joint efforts with TSMC to speed up AI, high‑performance computing and advanced semiconductor development. The collaboration adds certified electronic design automation flows for TSMC’s A14 process, agentic AI engineering workflows, multi‑die packaging support, co‑packaged optics and expanded 2nm silicon IP. Michael Buehler‑Garcia of Synopsys…
Key points
- Synopsys and TSMC certified design flows for TSMC’s A14 process, covering digital and analog designs.
- Agentic AI tools such as Fusion Compiler and 3DIC Compiler now automate analog, digital and multi‑die workflows on A14.
- Co‑packaged optics and integrated voltage regulator co‑design are enabled on TSMC’s CoWoS‑S and CoWoS technology via a unified flow.
The companies highlighted several concrete milestones: certification of digital and analog flows on A14, device routing enablement for analog place‑and‑route, and the use of Fusion Compiler and 3DIC Compiler to apply large‑language‑model assistance across analog, digital and multi‑die design tasks. Integrated voltage regulators and co‑packaged optics are now co‑designed within a unified environment for CoWoS‑S and CoWoS technology, while silicon IP for N2P, N3P and other advanced nodes supports PCIe 7.0, HBM4, LPDDR6/5X/5, 224G Ethernet PHY and UCIe standards.
Synopsys and TSMC Expand AI Design Work to A14 and Co-Packaged Optics
Unite.AI · 23 September 2026
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