researchers report agent-based hls with rtl refinement speeds chip design 2.6×
A new arXiv paper investigates whether large‑language‑model agents can improve chip design by working at a higher abstraction level than traditional register‑transfer‑level (RTL) coding. The authors compare four workflows – direct RTL design, agent‑based high‑level synthesis (HLS) design, post‑compiler HLS refinement, and post‑HLS RTL refinement – and then combine the agent‑based HLS approach…
Key points
- AHRR (agent‑based hls + rtl refinement) achieved a 2.6× geometric‑mean speedup over direct rtl design.
- Evaluation covered 11 benchmark tasks on fpga platforms, comparing four design‑flow variants.
- Hls abstraction lets agents capture design knowledge; rtl refinement recovers low‑level optimizations.
Using field‑programmable gate arrays (FPGAs) as a convenient testbed, the study evaluates the methods on an eleven‑task benchmark suite that spans diverse design challenges. Across the suite, AHRR delivers a geometric‑mean speedup of 2.6× relative to the direct RTL baseline. The authors attribute the gain to HLS abstracting design knowledge that agents can exploit, while the subsequent RTL refinement recovers low‑level performance opportunities. All code and evaluation artifacts are released on GitHub for reproducibility.
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